1. Field of the Invention
This invention relates in general to an improved method of managing computer memory for computers and digital systems and, in particular, to the management of processor memory arrays with store protect keys by integrating storage protect keys (SP Keys) in main storage to share the same physical memory.
2. Description of Background
In past generations of digital and computer designs in the IBM z-Series architecture, there was provided a Store Protect Key (SP Key) which was a logical SP Key for every 4 KB of storage. Each SP key was 7 bits in length. The operating system, such as z/OS managed data access via these SP Keys. In a typical IBM z-Series system, having 512 GB of memory provided for main storage, this resulted in 128 million SP Keys. These keys were packages in prior systems with SRAM or a separate DRAM infrastructure.
As the technologies and designs have evolved, this is becoming increasingly more difficult. For example, there is a need to improve granularity and cost/performance in the memory storage capacity of advanced computer memory systems with higher density DRAM technology and packaging such as that provided by the memory described in IBM's “A high Reliability Memory Module with a Fault Tolerant Address and Common Bus”, U.S. Pat. No. 7,234,099, granted Jun. 19, 2007, based on a application filed by Kevin C. Gower et al. U.S.Ser. No. 10/413605 of Apr. 14, 2003, which is incorporated herein by reference.
What is needed is a method and hardware that allows for maintaining a single copy of data sets with a plurality of instances in a mainframe computer system with increasing storage needs.